Generally, it is known that fabricating so called "printed circuits" by a die-stamping technique, rather than the well known etching process, is more efficient and provides a product of improved quality at reduced cost in labor and materials. Also, it is known that miniature and subminiature photoflash arrays are severely restricted insofar as space for both circuitry paths and components of the printed circuit are concerned. Thus, a photoflash array adapted to die-stamping circuit fabrication and improved space for circuitry and components represents a desired goal for miniature structures.
One known printed circuit design for a photoflash array is set forth in a pending application bearing U.S. Ser. No. 277,797, filed June 29, 1981, and assigned to the assignee of the present application. Herein, the printed circuit has a common circuit forming the perimeter of the circuit board. Although such structures are not especially troublesome when the printed circuit is effected by an etching process, there are problems when die-stamping is emloyed. More specifically, a common circuit perimeter of the circuit board inhibits the removal of scrap material in a die-stamp operation since there are no free edges of scrap for grasping and thereby applying a removing force to the scrap material.
Also, the problems associated with limited space and miniaturized components is set forth in a pending application bearing U.S. Ser. No. 325,068, filed Nov. 25, 1981, and assigned to the assignee of the present application. Herein, the array utilizes a plurality of normally closed switches and clearly sets forth the problems associated with handling and fabricating these individual switches. Moreover, the suggested structure also includes so called "blind" sections wherein the scrap from a die-stamp operation must be pulled in an opposite direction for removal.